1. Field of the Invention
The present invention relates to an ESD protection circuit designed to protect ICs (Integrated Circuits) and LSIs (Large-Scale Integration Circuits) from ESD (Electrostatic Discharge).
2. Description of the Related Art
Various ESD protection circuits have hitherto been proposed. They are designed to protect semiconductor integrated circuits, such as ICs and LSIs, from high voltages resulting from ESD. Three types of conventional ESD protection circuits will be described, with reference to FIGS. 1 to 5.
FIG. 1 is a circuit diagram schematically showing a first conventional ESD protection circuit.
As FIG. 1 shows, the circuit comprises two pads 11 and 12, and a clamp circuit 14. An internal circuit 13 to be protected against ESD is connected to both pads 11 and 12. The clamp circuit 14 is provided between and connected to the pads 11 and 12. The clamp circuit comprises an NMOS transistor 18. The transistor 18 has its drain and source connected to the first pad 11 and the second pad 12, respectively. The gate and back gate of the transistor 18 are connected to source of the transistor 18.
How the circuit of FIG. 1 operates will be described with reference to FIG. 2. FIG. 2 is a graph representing the voltage-current characteristic of the NMOS transistor 18 shown in FIG. 1. In FIG. 2, the voltage V1 applied between the drain and source of the transistor 18 is plotted on the abscissa, and the current I1 flowing between the drain and source of the transistor 18 is plotted on the coordinate.
No high voltage due to ESD may be applied between the first and second pads 11 and 12 (region 1). In this case, no current flows between the drain and source of the NMOS transistor 18 of the clamp circuit 14. This is because the transistor 18 is not on (not conducting) since its gate and source are connected to each other and therefore remain at the same potential. Thus, the internal circuit 13 can operate in normal way.
When high voltage resulting from ESD is applied between the first and second pads 11 and 12 (region 2), the NMOS transistor 18 is turned on. As a result, the ESD charge passes from the first pad 11 to the second pad 12 via the clamp circuit 14. That is, no high voltage is applied to the internal circuit 13. In other words, the internal circuit 13 is protected.
The voltage-current characteristics of the NMOS transistor 18 exhibited in the region 2 will be described in detail. When a high voltage is applied between the drain and source of the NMOS transistor 18, the voltage across the drain-source path rises to the trigger voltage Vt1, causing a snap-back in the transistor NMOS 18, as illustrated in FIG. 2. The snap-back lowers the voltage to a hold voltage Vh. Then, a current can abruptly flow in the NMOS transistor 18.
The current flowing in the NMOS transistor 18 at this time is an off-current. The off-current flows from the drain to the source by virtue of a bipolar action. It is not an on-current that flows the channel of the transistor 18.
The ESD-protection circuit of the configuration shown in FIG. 1 should satisfy the following two design requirements. First, the withstand voltage of the internal circuit 13 (at which the circuit 13 may break down) must be higher than the trigger voltage Vt1 of the NMOS transistor 18. Second, the hold voltage Vh must be higher than the power-supply voltage Vdd of the internal circuit 13. The second requirement should be satisfied in order to prevent the clamp circuit 14 from turning on while the internal circuit 13 is operating in normal condition.
In recent years the technology of manufacturing semiconductor devices has advanced, making it possible to provide smaller and smaller semiconductor elements. Consequently, the gate withstand voltage of MOSFETs has much reduced. MOSFETs made by the 0.18 to 0.13-micron process, for example, have a trigger voltage Vt1 that is almost the same as the gate withstand voltage. Furthermore MOSFETs made by the 0.09-micron process have a trigger voltage Vt1 that is lower than the gate withstand voltage. In view of the microelectronic processes to be developed in the future, it will be difficult to satisfy the first design requirement specified above.
A second conventional ESD protection circuit will be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic representation of the second conventional ESD protection circuit 2.
This ESD protection circuit differs from the first conventional ESD protection circuit, only in that it has a time-constant circuit 23. Such a time-constant circuit is disclosed in, for example, U.S. Pat. No. 6,249,410 (Jun. 19, 2001) and illustrated in FIG. 4 of the U.S. patent.
The time-constant circuit 23 comprises a capacitor C and a resistor R. One electrode of the capacitor C is connected to the pad 11. The other electrode of the capacitor C is connected to the gate of the NMOS transistor 18. The resistor R is connected at one end to the gate of the NMOS transistor 18 and at the other end to the pad 12.
How the second conventional ESD protection circuit operates will be explained, with reference to FIG. 4. FIG. 4 is a graph representing the voltage-current characteristic of the NMOS transistor 18 shown in FIG. 3. In FIG. 4, the voltage V1 applied between the drain and source of the NMOS transistor 18 is plotted on the abscissa, and the current 11 flowing between the drain and source of the NMOS transistor 18 is plotted on the coordinate.
Unless a high voltage resulting from ESD is applied between the first and second pads 11 and 12, the clamp circuit 14 is off as in the circuit illustrated in FIG. 1. Hence, the internal circuit 13 need not be protected from high voltages and can operate in normal way.
When a high voltage resulting from ESD is applied between the first and second pads 11 and 12, the time-constant circuit 23 generates a pulse that remains at high level for a specified time. The pulse is supplied to gate of the NMOS transistor 18, turning the NMOS transistor 18 on. Thus, the clamp circuit is turned on.
The ESD charge resulting from electrostatic discharge (ESD) is therefore transferred to the second pad 12 through the clamp circuit 14. This protects the internal circuit 13 from the high voltage generated from the ESC. The specific time mentioned above is determined by the time constant that is the product of the capacitance of the capacitor C and the resistance of the resistor R.
The voltage-current characteristic that the NMOS transistor 18 has when a high voltage resulting from ESD is applied between the first pad 11 and the second pad 12 will be described in detail, with reference to FIG. 4.
In FIG. 4, the solid line 25 indicates the voltage-current characteristic that the NMOS transistor 18 exhibits when a current resulting from the ESD flows in the channel of the NMOS transistor 18. In other words, the NMOS transistor 18 has this characteristic while it remains on. The broken line 26 shown in FIG. 4 represents the voltage-current characteristic that the NMOS transistor 18 exhibits when snap-back occurs as in the first conventional ESD protection circuit. That is, the broken line 26 depicts the characteristic the NMOS transistor 18 has while it remains off. As the comparison of FIG. 4 with FIG. 2 reveals, a larger current can flow in the NMOS transistor 18 than in the first conventional ESD protection circuit. Thus, the second conventional ESD protection circuit can protect the internal circuit 13 more reliably than the first conventional ESD protection circuit. Note that the characteristic of the solid line 25 pertains to the on-current that flows in the channel formed between the source and drain of the NMOS transistor 18, unlike in the first conventional ESD protection circuit. The current that flows in the NMOS transistor 18 and changes as indicated by the broken line 26 is an off-current that does not flow in the channel due to a bipolar action.
As can be understood from the above, the second conventional ESD protection circuit utilizes the on-current of the NMOS transistor 18, not the off-current thereof. Therefore, the first design requirement that the withstand voltage of the internal circuit 13 must be higher than the trigger voltage Vt1 of the NMOS transistor 18 need not be taken into consideration to design the second conventional ESD protection circuit. It is difficult, however, to design the time-constant circuit 23 incorporated in the second conventional ESD protection circuit. That is, if the time constant (i.e., the product of the capacitance of the capacitor C and the resistance of the resistor R) is small, the on-time of the NMOS transistor 18 will be short, disabling the circuit 2 to protect the internal circuit 13 effectively. If the time constant is large, the on-time will be long, enabling the circuit 2 to protect the internal circuit effectively. To acquire a sufficiently large time constant, the circuit 23 must comprises a capacitor and a resistor that have a high capacitance and a high resistance, respectively. This will increase the size and manufacturing cost of the chip incorporating the circuit 2 and the internal circuit 13. This is particularly because one time-constant circuit should be provided for each pad provided in the chip.
A third conventional ESD protection circuit will be described with reference to FIG. 5. FIG. 5 is a schematic representation of this circuit 3. Such an ESD protection circuit is disclosed in Albert Z. H. Wang, ON-CHIP ESD PROTECTION FOR INTEGRATED CIRCUITS, An IC Design Perspective, FIG. 4–24, Kluwer Academic Publishers Group.
As FIG. 5 illustrates, the third conventional ESD protection circuit comprises a clamp circuit 14, a time-constant circuit 23, and an inverter circuit 30. The inverter circuit 30 comprises three inverters 30-1, 30-2 and 30-3. The inverters 30-1 to 30-3 are provided between the clamp circuit 14 and the time-constant circuit 23. The inverters 30-1 to 30-3 have their input terminals connected to one another, and their output terminals connected to one another.
The first inverter 30-1 comprises a PMOS transistor P-1 and an NMOS transistor N-1. The second inverter 30-2 comprises a PMOS transistor P-2 and an NMOS transistor N-2. The third inverter 30-3 comprises a PMOS transistor P-3 and an NMOS transistor N-3. The first inverter 30-1 has its input terminal connected to the node 24 of the time-constant circuit 23, and its output terminal connected to the input terminal of the second inverter 30-2. The output terminal of the second inverter 30-2 is connected to the input terminal of the third inverter 30-3. The output terminal of the third inverter 30-3 is connected to the gate of the NMOS transistor 18 incorporated in the clamp circuit 14.
How the third conventional ESD protection circuit operates will be explained. Assume that a high voltage generated from ESD is applied between the first pad 11 and the second pad 12. Then, the time-constant circuit 23 and the inverter circuit 30 cooperate, generating a signal. The signal is supplied to the clamp circuit 14. In the clamp circuit 14, the signal turns on the NMOS transistor 18. The ESD charge applied to the first pad 11 is thereby transferred to the second pad 12 via the clamp circuit 14. The internal circuit 13 is thus protected. The third conventional ESD protection circuit operates in the same way as the second conventional ESD protection circuit in other points.
Having the time-constant circuit 23, the conventional ESD protection circuit 3 has the same disadvantage as the conventional ESD protection circuit 2. Further, it is more disadvantageous than the circuit 2 in terms of size and manufacturing cost because it includes the inverter circuit 30.
As described above, the conventional ESD protection circuits cannot sufficiently protect the internal circuit, is difficult to design and manufacture in small size, and is disadvantageous in size and manufacturing cost.